1. Technical Field
The invention disclosed and claimed herein generally pertains to a latch or latch circuit adapted to perform both self test and functional tasks and operations. More particularly, the invention pertains to a latch of the above type wherein functional tasks include writing data into the latch from a Static Random Access Memory (SRAM) array. Even more particularly, the invention pertains to a latch of the above type wherein data bits of unknown state from the SRAM array are prevented from entering the latch, while data for self testing is allowed into the latch.
2. Description of Related Art
As is known by those of skill in the art, flush latches are commonly used to receive data from an array of SRAMs, such as to move data stored temporarily in an SRAM to more permanent storage. It is also known that certain types of SRAMs support partial writes and write throughs. A write through occurs when data written into an SRAM is immediately made available at the output thereof. A partial write occurs when only some of the bit locations of the SRAM are being written to. For example, it could be economical to write only four of eight bits associated with an ASIC to an SRAM. In this situation, data would not be written into some of the bit locations of the SRAM. Accordingly, the read mechanism cannot guarantee to the latch that the contents or states of these bit locations are correct. Herein, bits or bit levels of this type are referred to as “X” states. Generally, when only certain bits in the SRAM are being written to and are thus known, it will be desirable to update only the latches of those written bits. Bits in the SRAM that are not being written to should not be used to update their associated latches. Otherwise, the latch would be written with an unknown state or “X” state.
Those of skill in the art have frequently found it useful to provide groups or sequences of latches with an Automatic Built-in Self Testing (ABIST) capability. In one arrangement, a Multiple Input Shift Register (MISR) is used for this purpose. The MISR is operated to move self test data, or p-bit data, along a latch bus to a sequence of latches connected to the bus. It would be advantageous to provide a simplified latch that could be used in connection with an SRAM array, including SRAMs that supported partial writes and write throughs, wherein the latch also was adapted for use with self test procedures such as those referred to above.